The performance of a semiconductor device is greatly affected by the Critical Dimension (CD) of a gate. That is, as the CD of the gate is shortened, gate signals are transmitted well, so the desired functions of the device can be performed without errors. Further, as the CD of the gate is shortened, the size of the device is reduced, so the device can be highly integrated.
Accordingly, research has been actively studied to shorten the CD of the gate in the semiconductor device.
The CD of the gate can be determined depending on the efficiency of photolithography and etching processes.
Accordingly, in order to precisely form the CD of the gate, various attempts are introduced in the photolithography and etching processes.
For example, one attempt is to employ a photolithography process apparatus having an ArF light source (wavelength of 193 nm) instead of a photolithography process apparatus having a KrF light source (wavelength of 248 nm). However, since the photolithography process apparatus having the ArF light source is expensive, the process cost is increased.
In addition, the etching process requires the establishment of more advanced process conditions capable of satisfying the gate CD as well as small Line Edge Roughness (LER) characteristics for a profile after the etching process. However, such advanced process conditions have not yet been established.